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Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process.

Shusuke YoshimotoTakuro AmashitaShunsuke OkumuraKoji NiiMasahiko YoshimotoHiroshi Kawaguchi
Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2012)
Keyphrases
  • error resilient
  • bit errors
  • bitstream
  • coding scheme
  • image transmission
  • high speed
  • bit rate
  • wavelet coefficients
  • error resilience