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0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
Yohei Nakata
Shunsuke Okumura
Hiroshi Kawaguchi
Masahiko Yoshimoto
Published in:
IPSJ Trans. Syst. LSI Des. Methodol. (2012)
Keyphrases
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caching scheme
software architecture
management system
power consumption
query processing
garbage collection
test cases
data transmission
parallel architecture
industry standard
cache invalidation
database systems
data management
times faster
multithreading
memory subsystem