A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.
Shusuke YoshimotoMasaharu TeradaShunsuke OkumuraToshikazu SuzukiShinji MiyanoHiroshi KawaguchiMasahiko YoshimotoPublished in: ASP-DAC (2013)
Keyphrases
- low power
- power consumption
- cmos technology
- low cost
- high speed
- power reduction
- nm technology
- single chip
- high power
- wireless transmission
- vlsi architecture
- digital signal processing
- vlsi circuits
- low power consumption
- access control
- power saving
- logic circuits
- gate array
- mixed signal
- power management
- power dissipation
- delay insensitive
- image sensor
- random access
- energy saving