Thiem Van Chu

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 43

Top Topics

Combinatorial Optimization

Annealing Algorithm

Top Venues

Publications

Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE (2024)
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE (2024)
Philippos Papaphilippou, Thiem Van Chu
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers. IEEE Trans. Computers 73 (5) (2024)
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024)
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC (2024)
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO (2024)
Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR (2024)
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS (2024)
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12 (2024)
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE (2024)
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE (2024)
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12 (2024)
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG (2023)
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits (2023)
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR (2023)
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC (2023)
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106 (12) (2023)
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM (2023)
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS (2023)
Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu
An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration. IEEE Access 11 (2023)
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Anas, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC (2023)
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
Multicoated Supermasks Enhance Hidden Networks. ICML (2022)
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops (2022)
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. (12) (2022)
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC (2022)
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11 (2) (2021)
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11 (2) (2021)
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS (2021)
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT (2021)
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR (2020)
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR (2020)
Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. FPGA (2020)
Thiem Van Chu, Kenji Kise
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes. IEICE Trans. Inf. Syst. (10) (2019)
Thiem Van Chu, Kenji Kise
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. FPL (2018)
Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. FCCM (2018)
Susumu Mashimo, Thiem Van Chu, Kenji Kise
High-Performance Hardware Merge Sorter. FCCM (2017)
Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise
Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip. MCSoC (2017)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. 10 (4) (2017)
Susumu Mashimo, Thiem Van Chu, Kenji Kise
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News 44 (4) (2016)
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS (2016)
Takuma Usui, Thiem Van Chu, Kenji Kise
A Cost-Effective and Scalable Merge Sorter Tree on FPGAs. CANDAR (2016)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Ultra-fast NoC emulation on a single FPGA. FPL (2015)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM (2015)
Thiem Van Chu, Shimpei Sato, Kenji Kise
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC (2014)
Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise
Ultrasmall: The smallest MIPS soft processor. FPL (2014)