Shimpei Sato

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 39

Top Topics

Similarity Metric

Speculative Execution

Top Venues

IEICE Trans. Inf. Syst.

Publications

Shimpei Sato, Kunio Kojima, Naoki Hiraoka, Kei Okada, Masayuki Inaba
Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints. IROS (2023)
Takuma Hiraoka, Shimpei Sato, Naoki Hiraoka, Annan Tang, Kunio Kojima, Kei Okada, Masayuki Inaba, Koji Kawasaki
Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid. IROS (2023)
Shimpei Sato, Yuta Kojio, Yohei Kakiuchi, Kunio Kojima, Kei Okada, Masayuki Inaba
Robust Humanoid Walking System Considering Recognized Terrain and Robots' Balance. IROS (2022)
Yohei Kakiuchi, Yuta Kojio, Noriaki Imaoka, Daiki Kusuyama, Shimpei Sato, Yutaro Matsuura, Takeshi Ando, Masayuki Inaba
Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers. Humanoids (2022)
Shimpei Sato, Yuta Kojio, Kunio Kojima, Fumihito Sugai, Yohei Kakiuchi, Kei Okada, Masayuki Inaba
Drop Prevention Control for Humanoid Robots Carrying Stacked Boxes. IROS (2021)
Naoto Soga, Shimpei Sato, Hiroki Nakahara
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. (8) (2021)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. (12) (2021)
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. (12) (2020)
Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops (2020)
Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara
A Table Look-Up Based Ternary Neural Network Processor. ISMVL (2020)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM (2020)
Shimpei Sato, Kano Akagi, Atsushi Takahashi
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC (2019)
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. (5) (2019)
Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
Noise Convolutional Neural Networks and FPGA Implementation. ISMVL (2019)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. (5) (2019)
Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA (2019)
Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL (2019)
Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig (2019)
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. ISCAS (2019)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART (2018)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL (2018)
Shimpei Sato, Ryohei Kobayashi, Kenji Kise
ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. IEICE Trans. Inf. Syst. (2) (2018)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
-Means Clustering Using a High-Level Synthesis Design. IEICE Trans. Inf. Syst. (2) (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART (2018)
Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL (2018)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA (2018)
Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI (2018)
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. (2) (2018)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL (2018)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT (2017)
Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL (2017)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. 10 (4) (2017)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
All binarized convolutional neural network and its implementation on an FPGA. FPT (2017)
Shimpei Sato, Yukinori Sato, Toshio Endo
Investigating potential performance benefits of memory layout optimization based on roofline model. SEPS@SPLASH (2015)
Shimpei Sato, Kenji Kise
ArchHDL: A Novel Hardware RTL Design Environment in C++. ARC (2015)
Yukinori Sato, Shimpei Sato, Toshio Endo
Exana: an execution-driven application analysis tool for assisting productive performance tuning. SEPS@SPLASH (2015)
Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise
Effective Parallel Simulation of ArchHDL under Manycore Environment. CANDAR (2015)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Ultra-fast NoC emulation on a single FPGA. FPL (2015)
Thiem Van Chu, Shimpei Sato, Kenji Kise
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM (2015)
Thiem Van Chu, Shimpei Sato, Kenji Kise
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC (2014)
Yuichiro Tanaka, Shimpei Sato, Kenji Kise
The Ultrasmall soft processor. SIGARCH Comput. Archit. News 41 (5) (2013)
Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC (2010)
Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC (2010)
Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT (2009)