Masayuki Shimoda

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 22

Top Topics

Convolutional Neural Network

Fpga Implementation

Top Venues

IEICE Trans. Inf. Syst.

Publications

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. ISCAS (2024)
Takafumi Tanaka, Masayuki Shimoda
Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks. J. Opt. Commun. Netw. 15 (12) (2023)
Masayuki Shimoda, Takafumi Tanaka
Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks. ECOC (2021)
Takafumi Tanaka, Masayuki Shimoda
Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning. ECOC (2021)
Masayuki Shimoda, Youki Sada, Hiroki Nakahara
FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. 93 (5) (2021)
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. (12) (2020)
Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops (2020)
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL (2019)
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC (2019)
Masayuki Shimoda, Youki Sada, Hiroki Nakahara
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC (2019)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. (5) (2019)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. (5) (2019)
Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA (2019)
Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL (2019)
Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig (2019)
Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT (2019)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL (2018)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
All binarized convolutional neural network and its implementation on an FPGA. FPT (2017)
Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. FPL (2017)