A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA.
Youki SadaMasayuki ShimodaAkira JingujiHiroki NakaharaPublished in: FPT (2019)
Keyphrases
- hardware architecture
- data flow
- image segmentation
- database machine
- software implementation
- hardware implementation
- segmentation algorithm
- hardware design
- design methodology
- hardware architectures
- segmentation method
- fully automatic
- real time
- medical images
- level set
- dedicated hardware
- management system
- pipelined architecture
- multiscale
- region growing
- dynamic reconfiguration
- image analysis
- fpga implementation
- fpga technology
- high speed
- field programmable gate array
- shape prior
- energy function
- sparse data
- control flow
- parallel architecture
- parallel processing
- reconfigurable hardware
- xilinx virtex
- low cost
- parallel computing
- object segmentation
- high dimensional
- software architecture
- sparse representation
- systolic array
- edge detection