Takefumi Miyoshi

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 5

Top Topics

Perspective Camera

Highly Flexible

Top Venues

IEICE Trans. Inf. Syst.

Publications

Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. ICFPT (2023)
Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Ryo Matsuda, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro
A Fully Pipelined Architecture of Quantum-Classical Interface for Realizing Fault-Tolerant Quantum Computer. QCE (2023)
Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi
A state vector quantum simulator working on FPGAs with extensible SATA storage. ICFPT (2023)
Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro
FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs. FPL (2022)
Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo
Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. HEART (2017)
Abraham Monrroy, Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Takefumi Miyoshi, Satoshi Funada
Hexa Cam: An FPGA-Based Multi-view Camera System. CPSNA (2015)
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. IEICE Trans. Inf. Syst. (12) (2015)
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. CANDAR (2013)
Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga
A fast handshake join implementation on FPGA with adaptive merging network. SSDBM (2013)
Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga
Design and Implementation of a Handshake Join Architecture on FPGA. IEICE Trans. Inf. Syst. (12) (2012)
Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga
FLAT: a GPU programming framework to provide embedded MPI. GPGPU@ASPLOS (2012)
Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga
Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA. MCSoC (2012)
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
Using Cacheline Reuse Characteristics for Prefetcher Throttling. IEICE Trans. Inf. Syst. (12) (2012)
Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga
Throttling Control for Bufferless Routing in On-chip Networks. MCSoC (2012)
Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. ICNC (2011)
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. 1 (2) (2011)
Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga
A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine. FPL (2011)
Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga
An Implementation of Handshake Join on FPGA. ICNC (2011)
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. ICNC (2011)
Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. IEICE Trans. Inf. Syst. (12) (2011)
Qin Wang, Junichi Ohmura, Axida Shan, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. ICNC (2010)
Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC (2010)
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
An Efficient Path Setup for a Photonic Network-on-Chip. ICNC (2010)
Cisse Ahmadou Dit Adi, Ping Qiu, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip. IWIA (2010)
Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC (2010)
Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC (2010)
Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe
Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. ReConFig (2009)
Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT (2009)
Takefumi Miyoshi, Nobuhiko Sugino
Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption. SIGARCH Comput. Archit. News 35 (5) (2007)
Takefumi Miyoshi, Nobuhiko Sugino
Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation. IEICE Trans. Inf. Syst. (12) (2007)
Takefumi Miyoshi, Nobuhiko Sugino
Unified Phase Compiler by Use of 3-D Representation Space. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)