Kaijie Wei

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 18

Top Topics

Stereo Matching

Fpga Implementation

Source Separation

Top Venues

IEICE Trans. Inf. Syst.

Publications

Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi
A data compressor for FPGA-based state vector quantum simulators. HEART (2024)
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano
A cost/power efficient storage system with directly connected FPGA and SATA disks. MCSoC (2023)
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. ICFPT (2023)
Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board. COOL CHIPS (2023)
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106 (3) (2023)
Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi
A state vector quantum simulator working on FPGAs with extensible SATA storage. ICFPT (2023)
Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board. CANDAR (2022)
Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
An FPGA off-loading of HARK sound source localization. CANDARW (2022)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12 (2) (2022)
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART (2022)
Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory. CANDARW (2022)
Kaijie Wei, Koki Honda, Hideharu Amano
An implementation methodology for Neural Network on a Low-end FPGA Board. Int. J. Netw. Comput. 11 (2) (2021)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) (2021)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. (12) (2021)
Kaijie Wei, Koki Honda, Hideharu Amano
An implementation methodology for Neural Network on a Low-end FPGA Board. CANDAR (2020)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) (2020)
Koki Honda, Kaijie Wei, Hideharu Amano
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. MCSoC (2019)
Kaijie Wei, Koki Honda, Hideharu Amano
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks. FPT (2018)