Masatoshi Arai

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 6

Top Topics

High Scalability

Occlusion Handling

Stereo Matching

Top Venues

IEICE Trans. Inf. Syst.

CANDAR (Workshops)

Int. J. Netw. Comput.

Publications

Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106 (3) (2023)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12 (2) (2022)
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART (2022)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) (2021)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. (12) (2021)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) (2020)
Masato Tsukada, Chisato Funayama, Masatoshi Arai, Charles Dubout
Face Image Enhancement Taking into Account Lighting Behavior on a Face. CAIP (2) (2011)
Takeharu Goji Etoh, Son Dao Vu Truong, Toshiaki Koike-Akino, Toshiro Akino, Kenji Nishi, Masatoshi Kureta, Masatoshi Arai
Ultra-High-Speed Image Signal Accumulation Sensor. Sensors 10 (4) (2010)
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. CIT (2007)
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
A High Speed License Plate Recognition System on an FPGA. FPL (2007)
Masatoshi Arai, Tohru Nakagawa, Hajime Kitagawa
A neural inverse function for automatic test pattern generation using strictly digital neural networks. VTS (1993)