Conformance and mirroring for timed asychronous circuits.

Bin Zhou Tomohiro Yoneda Bernd-Holger Schlingloff

Published in: ASP-DAC (2001)

Keyphrases

petri net
high speed
delay insensitive
timed automata
logic circuits
vlsi circuits
analog circuits
digital circuits
tunnel diode
databases
circuit design
discrete event
learning environment
logic synthesis
analog vlsi
case study
learning algorithm