Verification of asynchronous circuits based on zero-suppressed BDDs.
Koichi MasukuraMinoru TomisakaTomohiro YonedaPublished in: Systems and Computers in Japan (2001)
Keyphrases
- asynchronous circuits
- binary decision diagrams
- model checking
- process algebra
- delay insensitive
- temporal logic
- boolean functions
- formal verification
- formal specification
- verification method
- decision diagrams
- planning problems
- timed automata
- formal methods
- knowledge compilation
- association rules
- concurrent systems
- genetic algorithm