Verification of Bounded Delay Asynchronous Circuits with Timed Traces.

Tomohiro Yoneda Bin Zhou Bernd-Holger Schlingloff

Published in: AMAST (1998)

Keyphrases

asynchronous circuits
model checking
timed automata
process algebra
petri net
delay insensitive
temporal logic
verification method
markov chain
finite state machines
data sets
genetic algorithm
low cost
log files
asymptotically optimal
processor sharing