High Level Synthesis of Timed Asynchronous Circuits.
Tomohiro YonedaAtsushi MatsumotoManabu KatoChris J. MyersPublished in: ASYNC (2005)
Keyphrases
- asynchronous circuits
- high level synthesis
- model checking
- timed automata
- petri net
- delay insensitive
- process algebra
- parallel architecture
- design space exploration
- temporal logic
- discrete event
- computer vision
- formal specification
- image processing
- web services
- real world
- computer systems
- higher order
- scheduling problem
- pairwise
- multi agent systems