Hazard Checking of Timed Asynchronous Circuits Revisited.

Frédéric Béal Tomohiro Yoneda Chris J. Myers

Published in: ACSD (2007)

Keyphrases

asynchronous circuits
model checking
delay insensitive
process algebra
petri net
timed automata
verification method
finite state machines
risk assessment
machine learning
discrete event
temporal logic
consistency checking
distributed systems
similarity measure
computer vision
information retrieval