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Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.

Curtis A. NelsonChris J. MyersTomohiro Yoneda
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
  • asynchronous circuits
  • delay insensitive
  • process algebra
  • model checking
  • genetic algorithm
  • lightweight
  • petri net
  • neural network
  • multiscale
  • levels of abstraction