Verification of timed circuits with failure-directed abstractions.
Hao ZhengChris J. MyersDavid WalterScott LittleTomohiro YonedaPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2006)
Keyphrases
- asynchronous circuits
- model checking
- colored petri nets
- delay insensitive
- timed automata
- petri net
- verification method
- analog circuits
- face verification
- functional verification
- failure prediction
- formal verification
- failure rate
- high level
- logic circuits
- search algorithm
- failure recovery
- databases
- data sets
- vlsi circuits
- real time