Verification of Timed Circuits with Failure Directed Abstractions.
Hao ZhengChris J. MyersDavid WalterScott LittleTomohiro YonedaPublished in: ICCD (2003)
Keyphrases
- asynchronous circuits
- model checking
- verification method
- petri net
- timed automata
- colored petri nets
- delay insensitive
- high speed
- concurrent systems
- high level
- formal verification
- circuit design
- formal analysis
- failure rate
- digital circuits
- analog circuits
- finite state machines
- data sets
- component failures
- analog vlsi
- failure detection
- formal methods
- temporal logic
- information systems
- artificial intelligence