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A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
Xuan-Tu Tran
Yvain Thonnart
Jean Durupt
Vincent Beroulle
Chantal Robach
Published in:
NOCS (2008)
Keyphrases
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hardware software co design
hardware design
network on chip
design methodology
hardware architecture
efficient implementation
packet switched
real time
design process
computer architecture
cmos technology
multi processor