An efficient hardware architecture for inter-prediction in H.264/AVC encoders.
Nam-Khanh DangXuan-Tu TranAlain MerirotPublished in: DDECS (2014)
Keyphrases
- parallel implementation
- hardware architecture
- hardware implementation
- video encoder
- video coding
- rate distortion
- compression efficiency
- hardware architectures
- intra coding
- low complexity
- mode decision
- scalable video coding
- field programmable gate array
- low cost
- inter layer
- compressed domain
- video compression
- bit rate
- markov random field
- error propagation
- prediction error
- associative memory
- bitstream
- neural network
- block matching motion estimation