Olivier Billoint

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 17

Top Topics

Integrated Circuit

Manifold Embedding

Ultra Low Power

Energy Efficiency

Top Venues

Publications

Olivier Billoint, Simon Martin, J. Laguerre, L. Hosier, Jean Coignus, Catherine Carabasse, François Andrieu, Laurent Grenouillet
Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome CBL-induced Bank Size Limitations. IMW (2024)
J. Laguerre, Marc Bocquet, Olivier Billoint, S. Martin, Jean Coignus, Catherine Carabasse, T. Magis, T. Dewolf, François Andrieu, Laurent Grenouillet
Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes. IMW (2023)
Behnam Samadpoor Rikan, Philipp Häfliger, Gerald Cibrario, Olivier Billoint, Mehdi Mouhdach
Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process. MWSCAS (2021)
Laurent Grenouillet, Niccolo Castellani, Alain Persico, V. Meli, S. Martin, Olivier Billoint, R. Segaud, Stefania Bernasconi, C. Pellissier, Carine Jahan, Christelle Charpin-Nicolle, P. Dezest, Catherine Carabasse, Paul Besombes, S. Ricavy, N. P. Tran, A. Magalhaes-Lucas, A. Roman, C. Boixaderas, T. Magis, Messaoud Bedjaoui, M. Tessaire, A. Seignard, F. Mazen, S. Landis, Elisa Vianello, Gabriel Molas, Fred Gaillard, Julien Arcamone, E. Nowak
16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors. IMW (2021)
Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. DATE (2020)
Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 3DIC (2019)
Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS (2018)
François Andrieu, Perrine Batude, Laurent Brunet, Claire Fenouillet-Béranger, Didier Lattard, Sébastien Thuries, Olivier Billoint, R. Fournel, Maud Vinet
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. ICICDT (2018)
Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS (2017)
Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. ISVLSI (2017)
Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits. Microelectron. J. 60 (2017)
Claire Fenouillet-Béranger, Perrine Batude, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, M.-P. Samson, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Gerald Cibrario, Maud Vinet
Recent advances in 3D VLSI integration. ICICDT (2016)
C. Santos, Pascal Vivet, Sébastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, L. Wang
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes. 3DIC (2016)
Melanie Brocard, Guillaume Berhault, Sébastien Thuries, Fabien Clermidy, Perrine Batude, Claire Fenouillet-Béranger, Laurent Brunet, François Andrieu, Fabien Deprat, Joris Lacord, Olivier Rozeau, Gerald Cibrario, Olivier Billoint
Impact of intermediate BEOL technology on standard cell performances of 3D VLSI. ESSDERC (2016)
Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Guillaume Berhault, Cristiano Lopes Dos Santos, Gerald Cibrario, Fabien Clermidy, Daniel Gitlin, Olivier Faynot
Opportunities brought by sequential 3D CoolCube™ integration. ESSDERC (2016)
Gerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sébastien Thuries, Alexandre Valentian
From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose. 3DIC (2016)
Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, A. Fustier, Julien Michallet, Olivier Faynot, Ogun Turkyilmaz, Jean-Frédéric Christmann, Sébastien Thuries, Fabien Clermidy
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. DATE (2015)
Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS (2015)
Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits. ISVLSI (2015)
Edith Beigné, Jean-Frédéric Christmann, Alexandre Valentian, Olivier Billoint, Esteve Amat, Dominique Morche
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. ESSDERC (2015)
Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy
Intermediate BEOL process influence on power and performance for 3DVLSI. 3DIC (2015)
Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sébastien Thuries, Fabien Clermidy
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges. ISPD (2015)
Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50 (1) (2015)
Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
Compact interconnect approach for networks of neural cliques using 3D technology. VLSI-SoC (2015)
Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC (2014)
Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
3DCoB: A new design approach for Monolithic 3D Integrated circuits. ASP-DAC (2014)
Fabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon
3D technologies for reconfigurable architectures. ReCoSoC (2014)
Gerald Cibrario, Marjorie Gary, Fabien Gays, Karim Azizi-Mourier, Olivier Billoint, Ogun Turkyilmaz, Olivier Rozeau
A high-level design rule library addressing CMOS and heterogeneous technologies. ICICDT (2014)
Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE (2013)
Jani Mäkipää, Olivier Billoint
FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? ISCAS (2013)
Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard
Distributed clock generator for synchronous SoC using ADPLL network. CICC (2013)
Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig (2013)