Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.
Dimitri GalaykoChuan ShanEldar ZianbetovMohammad JavidanAnton KorniienkoFrançois AnceauOlivier BillointÉric ColinetElena BlokhinaJérôme JuillardPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2019)