François Anceau

Publication Activity (10 Years)

Years Active: 1989-2019
Publications (10 Years): 1

Top Venues

NEWCAS

ISCAS

IEEE Trans. Circuits Syst. II Express Briefs

ReConFig

Grenoble Institute of Technology, France (PHD)

Education History

Grenoble Institute of Technology, France

PHD

Publications

Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS (2015)
Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov
A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC (2014)
Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset
Complexity in heterogeneous systems on chips: Dsign and analysis challenges. ISCAS (2014)
Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov
"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS (2014)
Chuan Shan, Dimitri Galayko, François Anceau
On-chip clock error characterization for clock distribution system. ISVLSI (2013)
Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard
Distributed clock generator for synchronous SoC using ADPLL network. CICC (2013)
Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig (2013)
Chuan Shan, Dimitri Galayko, François Anceau
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. NEWCAS (2012)
Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard
A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. ISCAS (2011)
Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard
All-digital PLL array provides reliable distributed clock for SOCs. ISCAS (2011)
Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard
A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS (2011)
Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT (2011)
François Anceau
Formal Verification: A Significant Step Towards Zero Deffect VLSI Design. IFIP Congress (1989)

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Publication Activity (10 Years)

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François Anceau