On-chip clock error characterization for clock distribution system.

Chuan Shan Dimitri Galayko François Anceau

Published in: ISVLSI (2013)

Keyphrases

high speed
power consumption
duty cycle
low cost
probability distribution
error bounds
spatial distribution
low power
error rate
error analysis
input output
steady state
neural network
estimation error
high density
extreme values
analog vlsi
lower bound