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FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Chuan ShanEldar ZianbetovMohammad JavidanFrançois AnceauMehdi TerosietSylvain FeruglioDimitri GalaykoOlivier RomainÉric ColinetJérôme Juillard
Published in: FPT (2011)
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