Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction.
Alexandre ValentianEdith BeignéPublished in: ESSCIRC (2007)
Keyphrases
- high speed
- power reduction
- cmos technology
- power consumption
- power dissipation
- low power
- single phase
- leakage current
- duty cycle
- low voltage
- energy dissipation
- power management
- multiple input
- field effect transistors
- decision trees
- maximum number
- electronic circuits
- logic circuits
- short circuit
- nm technology
- delay insensitive
- power saving
- analog circuits
- computational power
- control system
- evolutionary algorithm