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33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.

Weier WanRajkumar KubendranSukru Burc EryilmazWenqiang ZhangYan LiaoDabin WuStephen R. DeissBin GaoPriyanka RainaSiddharth JoshiHuaqiang WuGert CauwenberghsH.-S. Philip Wong
Published in: ISSCC (2020)
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