Login / Signup
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.
Saeroonter Oh
Jeongha Park
S. Simon Wong
H.-S. Philip Wong
Published in:
ISQED (2010)
Keyphrases
</>
logic synthesis
digital circuits
data analysis
design process
power consumption
chip design
logic programming
power dissipation
power reduction
logic circuits
image segmentation
case study
embedded systems
nm technology
analog circuits
low power
mobile devices
relational databases