Sayeef S. Salahuddin

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 18

Top Topics

Gpu Accelerated

Combinatorial Optimization

Contrastive Divergence

Leakage Current

Top Venues

Publications

Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa, Sayeef S. Salahuddin, Zhi Yao
FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices. Comput. Phys. Commun. 290 (2023)
Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Y.-K. Lin, Chenming Hu, Sayeef S. Salahuddin
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack. VLSI Technology and Circuits (2023)
Nirmaan Shanker, Li-Chen Wang, Suraj Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin
On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs. VLSI Technology and Circuits (2022)
Chetan K. Dabhi, Girish Pahwa, Sayeef S. Salahuddin, Chenming Hu
Compact Model for Trap Assisted Tunneling based GIDL. DRC (2022)
Richard A. Gottscho, Edlyn V. Levine, Tsu-Jae King Liu, Paul C. McIntyre, Subhasish Mitra, Boris Murmann, Jan M. Rabaey, Sayeef S. Salahuddin, Willy C. Shih, H.-S. Philip Wong
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. CoRR (2022)
Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa, Sayeef S. Salahuddin, Zhi Yao
FerroX : A GPU-accelerated, 3D Phase-Field Simulation Framework for Modeling Ferroelectric Devices. CoRR (2022)
Ava J. Tan, Li-Chen Wang, Yu-Hung Liao, Jong-Ho Bae, Chenming Hu, Sayeef S. Salahuddin
Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET. DRC (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108 (4) (2020)
Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu
GC-eDRAM design using hybrid FinFET/NC-FinFET. ISLPED (2020)
Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu
Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs. ISCAS (2020)
Saavan Patel, Lili Chen, Philip Canoza, Sayeef S. Salahuddin
Ising Model Optimization Problems on a FPGA Accelerated Restricted Boltzmann Machine. CoRR (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
Scanning the Issue. Proc. IEEE 108 (4) (2020)
Saavan Patel, Philip Canoza, Sayeef S. Salahuddin
Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization. CoRR (2020)
Justin C. Wong, Sayeef S. Salahuddin
Negative Capacitance Transistors. Proc. IEEE 107 (1) (2019)
Saavan Patel, Sayeef S. Salahuddin
Combining Learned Representations for Combinatorial Optimization. CoRR (2019)
Sandeep Kumar Samal, Sourabh Khandelwal, Asif I. Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim
Full chip power benefits with negative capacitance FETs. ISLPED (2017)
Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC (2017)
Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif I. Khan, Sayeef S. Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan
Nonvolatile memory design based on ferroelectric FETs. DAC (2016)
Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay
Electrothermal analysis of spin-transfer-torque random access memory arrays. ACM J. Emerg. Technol. Comput. Syst. 9 (2) (2013)
Youngki Yoon, Sayeef S. Salahuddin
Performance assessment of partially unzipped carbon nanotube field-effect transistors. NANOARCH (2011)
Subho Chatterjee, Sayeef S. Salahuddin, Saibal Mukhopadhyay
Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. IEEE Trans. Circuits Syst. II Express Briefs (3) (2010)
Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 18 (12) (2010)
Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. ISLPED (2010)
Jing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. CICC (2008)
Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC (2008)
Md. Kamrul Hasan, Sayeef S. Salahuddin, M. Rezwan Khan
Reducing signal-bias from MAD estimated noise level for DCT speech enhancement. Signal Process. 84 (1) (2004)