Lawrence T. Clark

Publication Activity (10 Years)

Years Active: 1990-2022
Publications (10 Years): 16

Top Topics

Integrated Circuit

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Vinay Vashishtha, Lawrence T. Clark
ASAP5: A predictive PDK for the 5 nm node. Microelectron. J. 126 (2022)
Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella
Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology. ISCAS (2022)
Vinay Vashishtha, Lawrence T. Clark
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. Microelectron. J. 107 (2021)
Lawrence T. Clark, James Adams, Keith E. Holbert
Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory. Integr. 65 (2019)
John Brunhaver, Richard Uhrie, Lawrence T. Clark
Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala, John Brunhaver
Physically Unclonable Functions Using Foundry SRAM Cells. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala
SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark
ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper. ICCAD (2017)
Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark
Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. ISQED (2017)
Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark
Robust 7-nm SRAM design on a predictive PDK. ISCAS (2017)
Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang
Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit. MSE (2017)
Lawrence T. Clark, James Adams, Keith E. Holbert
Integrated circuit identification and true random numbers using 1.5-transistor flash memory. ISQED (2017)
Lawrence T. Clark, Vinay Vashishtha
Design with sub-10 nm FinFET technologies. CICC (2017)
Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. Holbert
An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits. IEEE Trans. Computers 65 (2) (2016)
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53 (2016)
Srivatsan Chellappa, Lawrence T. Clark
SRAM-Based Unique Chip Identifier Techniques. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark
Delay and power tradeoffs for static and dynamic register files. ISCAS (2015)
Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth
A soft-error hardened process portable embedded microprocessor. CICC (2015)
Aymeric Privat, Lawrence T. Clark
Simple and accurate single event charge collection macro modeling for circuit simulation. ISCAS (2015)
Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark
Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation. ISQED (2015)
José M. de la Rosa, Patrick Chiang, Lawrence T. Clark
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark
Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. ISCAS (2015)
Lawrence T. Clark, Sandeep Shambhulingaiah
Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits. ISVLSI (2014)
Lawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan
Independent N and P process monitors for body bias based process corner correction. CICC (2014)
Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark
Methodology to optimize critical node separation in hardened flip-flops. ISQED (2014)
Aymeric Privat, Lawrence T. Clark, Hugh J. Barnaby
Transient response exploration of SRAM cell metastable states caused by ionizing radiation with 3D mixed mode simulation. ICECS (2014)
Robert Rogenmoser, Lawrence T. Clark
Reducing Transistor Variability for High Performance Low Power Chips. IEEE Micro 33 (2) (2013)
Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark
Low Complexity Out-of-Order Issue Logic Using Static Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Lawrence T. Clark, Samuel Leshner, George Tien
SRAM cell optimization for low AVT transistors. ISLPED (2013)
Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. CICC (2013)
Srivatsan Chellappa, Aritra Dey, Lawrence T. Clark
Improved circuits for microchip identification using SRAM mismatch. CICC (2011)
Lawrence T. Clark, David E. Pettit, Keith E. Holbert, Nathan D. Hindman
Validation of and delay variation in total ionizing dose hardened standard cell libraries. ISCAS (2011)
Satendra Kumar Maurya, Lawrence T. Clark
A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing. J. Low Power Electron. 7 (3) (2011)
Satendra Kumar Maurya, Lawrence T. Clark
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Lawrence T. Clark, Tai-Hua Chen, Vikas Chaudhary
Efficient voltage conversion for SRAM low standby power modes. ISCAS (2011)
Lawrence T. Clark, Vikas Chaudhary
Fast low power translation lookaside buffers using hierarchical NAND match lines. ISCAS (2010)
Satendra Kumar Maurya, Lawrence T. Clark
Fast and scalable priority encoding using static CMOS. ISCAS (2010)
Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski
Out-of-order issue logic using sorting networks. ACM Great Lakes Symposium on VLSI (2010)
Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert
Single event transient mitigation in cache memory using transient error checking circuits. CICC (2010)
Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark
In-situ characterization and extraction of SRAM variability. DAC (2010)
Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark
Reducing process variation impact on replica-timed static random access memory sense timing. Integr. 42 (4) (2009)
Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 44 (8) (2009)
Giby Samson, Lawrence T. Clark
Low-Power Race-Free Programmable Logic Arrays. IEEE J. Solid State Circuits 44 (3) (2009)
Satendra Kumar Maurya, Lawrence T. Clark
Low power fast and dense longest prefix match content addressable memory for IP routers. ISLPED (2009)
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark
Leakage Controlled Read Stable Static Random Access Memories. J. Comput. 3 (4) (2008)
Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili
Amorphous silicon logic circuits on flexible substrates. CICC (2008)
Jonathan R. Haigh, Lawrence T. Clark
High performance set associative translation lookaside buffers for low power microprocessors. Integr. 41 (4) (2008)
Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark
Critical race-free low-power nand match line content addressable memory tagged cache memory. IET Comput. Digit. Tech. 2 (1) (2008)
Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark
Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories. IEEE J. Solid State Circuits 43 (11) (2008)
Lawrence T. Clark, Ranjit Gharpurey, Payam Heydari
Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 43 (8) (2008)
Sayeed A. Badrudduza, Lawrence T. Clark
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. CICC (2007)
Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. VLSI Design (2007)
Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen
A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. CICC (2007)
Yu Cao, Lawrence T. Clark
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Vikas Chaudhary, Lawrence T. Clark
Low-power high-performance nand match line content addressable memories. IEEE Trans. Very Large Scale Integr. Syst. 14 (8) (2006)
Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen
An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage. IEEE J. Solid State Circuits 41 (10) (2006)
Giby Samson, Lawrence T. Clark
A 0.13 μm Low-power Race-free Programmable Logic Array. CICC (2006)
Giby Samson, Lawrence T. Clark
Circuit architecture for low-power race-free programmable logic arrays. ACM Great Lakes Symposium on VLSI (2006)
Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark
Subthreshold to Above Threshold Level Shifter Design. J. Low Power Electron. 2 (2) (2006)
Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark
Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power. J. Low Power Electron. 2 (3) (2006)
Jinhui Chen, Lawrence T. Clark, Yu Cao
Robust Design of High Fan-In/Out Subthreshold Circuits. ICCD (2005)
Kyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark
Reducing power in flexible a-Si digital circuits while preserving state. CICC (2005)
Lawrence T. Clark, Franco Ricci, Manish Biyani
Low standby power state storage for sub-130-nm technologies. IEEE J. Solid State Circuits 40 (2) (2005)
Yu Cao, Lawrence T. Clark
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. DAC (2005)
Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. IEEE J. Solid State Circuits 40 (5) (2005)
Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty
Managing standby and active mode leakage power in deep sub-micron design. ISLPED (2004)
Lawrence T. Clark, M. Morrow, W. Brown
Reverse-body bias and supply collapse for low effective standby power. IEEE Trans. Very Large Scale Integr. Syst. 12 (9) (2004)
Lawrence T. Clark
Trends and challenges for wireless embedded DSPs. CICC (2003)
Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson
Reducing translation lookaside buffer active power. ISLPED (2003)
Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci
Standby power management for a 0.18µm microprocessor. ISLPED (2002)
Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch
An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J. Solid State Circuits 36 (11) (2001)
Lawrence T. Clark, Gregory F. Taylor
High fan-in circuit design. IEEE J. Solid State Circuits 31 (1) (1996)
Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik
A 150 MHz 0.6 μm BiCMOS superscalar microprocessor. IEEE J. Solid State Circuits 29 (12) (1994)
Arun Rao, Mark R. Walker, Lawrence T. Clark, Lex A. Akers, R. O. Grondin
VLSI Implementation of Neural Classifiers. Neural Comput. 2 (1) (1990)