Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.
Vineet AgrawalN. KeplerDavid KiddGokul KrishnanSamuel LeshnerT. BakishevD. ZhaoP. RanadeR. RoyM. WojkoLawrence T. ClarkRobert RogenmoserM. HoriTaiji EmaS. MoriwakiT. TsurutaT. YamadaJ. MitaniS. WakayamaPublished in: CICC (2013)
Keyphrases
- low power
- power consumption
- wireless transmission
- low cost
- high speed
- cmos technology
- high power
- single chip
- multi channel
- digital signal processing
- power saving
- image sensor
- logic circuits
- vlsi architecture
- vlsi circuits
- gate array
- mixed signal
- channel capacity
- power reduction
- low power consumption
- wireless channels
- real time
- data center
- parallel processing
- signal processing
- digital camera
- wireless communication