A low-power 2.5-GHz 90-nm level 1 cache and memory management unit.
Jonathan R. HaighMichael W. WilkersonJay B. MillerTimothy S. BeattyStephen J. StrazdusLawrence T. ClarkPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- low power
- memory management
- high speed
- power consumption
- low cost
- garbage collection
- cmos technology
- operating system
- memory hierarchy
- single chip
- hardware implementation
- memory access
- logic circuits
- vlsi circuits
- digital signal processing
- nm technology
- power reduction
- low power consumption
- computing environments
- power saving
- image sensor
- low voltage
- parallel computation
- mixed signal
- energy efficiency