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Single event transient mitigation in cache memory using transient error checking circuits.
Xiaoyin Yao
Lawrence T. Clark
Dan W. Patterson
Keith E. Holbert
Published in:
CICC (2010)
Keyphrases
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steady state
main memory
memory hierarchy
neural network
event detection
error bounds
processor core
virtual memory
error rate
random access memory
computational power
event recognition
power dissipation
read write
back end
prefetching
memory requirements