Rakshith Saligram

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 7

Top Topics

Hardware Software Partitioning

Cache Conscious

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Rakshith Saligram, Suman Datta, Arijit Raychowdhury
Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. ISLPED (2023)
Rakshith Saligram, Suman Datta, Arijit Raychowdhury
Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta
Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. VLSI Technology and Circuits (2022)
Rakshith Saligram, Suman Datta, Arijit Raychowdhury
CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. CICC (2021)
Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. CICC (2021)
Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. VLSI-SOC (2020)
Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. VLSI-SoC (Selected Papers) (2020)
Rakshith Saligram
Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG. ISED (2013)
Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. CoRR (2013)
Rakshith Saligram, T. R. Rakshith
Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate. ICACCI (2013)