James D. Meindl

Publication Activity (10 Years)

Years Active: 1986-2010
Publications (10 Years): 0

Publications

James D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali
Nanoelectronics in retrospect, prospect and principle. ISSCC (2010)
Azad Naeemi, James D. Meindl
Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD (2008)
Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC (2008)
Kaveh Shakeri, James D. Meindl
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Azad Naeemi, Reza Sarvari, James D. Meindl
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC (2007)
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD (2007)
Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC (2007)
Azad Naeemi, James D. Meindl
Carbon nanotube interconnects. ISPD (2007)
Muhannad S. Bakir, Bing Dang, James D. Meindl
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. CICC (2007)
Hiren D. Thacker, James D. Meindl
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. ITC (2006)
Kaveh Shakeri, James D. Meindl
Relative inductance extraction method. CICC (2004)
James W. Joyner, Payman Zarkesh-Ha, James D. Meindl
Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 12 (4) (2004)
Kaveh Shakeri, Muhannad S. Bakir, James D. Meindl
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. SoCC (2004)
Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills
Modeling technology impact on cluster microprocessor performance. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
James D. Meindl
Interconnect Opportunities for Gigascale Integration. IEEE Micro 23 (3) (2003)
James D. Meindl
Beyond Moore's Law: the interconnect era. Comput. Sci. Eng. 5 (1) (2003)
James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
Interconnect opportunities for gigascale integration. IBM J. Res. Dev. 46 (2-3) (2002)
Muhannad S. Bakir, Hollie A. Reed, Anthony V. Mule, Paul A. Kohl, Kevin P. Martin, James D. Meindl
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. CICC (2002)
Keith A. Bowman, Steven G. Duvall, James D. Meindl
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37 (2) (2002)
A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl
Electrical and optical clock distribution networks for gigascale microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 10 (5) (2002)
Kaveh Shakeri, James D. Meindl
A compact delay model for series-connected MOSFETs. ACM Great Lakes Symposium on VLSI (2002)
R. Murali, Lihui Wang, Blanca Austin, James D. Meindl
Low-power circuit advantages of the scaled accumulation FET. ISCAS (5) (2002)
Kaveh Shakeri, James D. Meindl
Temperature Variable Supply Voltage for Power Reduction. ISVLSI (2002)
Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
A physical model for the transient response of capacitively loaded distributed rlc interconnects. DAC (2002)
Keith A. Bowman, James D. Meindl
Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC (2001)
Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. ICCD (2001)
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
James D. Meindl
Special issue on limits of semiconductor technology. Proc. IEEE 89 (3) (2001)
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD (2001)
Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits 36 (4) (2001)
Lucian Codrescu, D. Scott Wills, James D. Meindl
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Trans. Computers 50 (1) (2001)
James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl
Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE 89 (3) (2001)
Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP (2000)
James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP (2000)
Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
James D. Meindl, Jeffrey A. Davis
The fundamental limit on binary switching energy for terascale integration (TSI). IEEE J. Solid State Circuits 35 (10) (2000)
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED (2000)
Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
Prediction of interconnect fan-out distribution using Rent's rule. SLIP (2000)
Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8 (3) (2000)
Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
A compact physical via blockage model. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI (2000)
Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl
Heterogeneous architecture models for interconnect-motivated system design. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Payman Zarkesh-Ha, Tony Mule, James D. Meindl
Characterization and modeling of clock skew with process variations. CICC (1999)
Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl
Exploring Microprocessor Architectures for Gigascale Integration. ARVLSI (1999)
James D. Meindl
XXI Century Gigascale Integration (GSI) : The Interconnect Problem. ARVLSI (1999)
Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl
A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits 34 (10) (1999)
Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
Minimum supply voltage for bulk Si CMOS GSI. ISLPED (1998)
Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. CICC (1998)
James D. Meindl
A history of low power electronics: how it began and where it's headed. ISLPED (1997)
Xinghai Tang, Vivek De, James D. Meindl
Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. Very Large Scale Integr. Syst. 5 (4) (1997)
Vivek De, James D. Meindl
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED (1996)
Xinghai Tang, Vivek De, James D. Meindl
Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED (1996)
Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
Circuit techniques for low-power CMOS GSI. ISLPED (1996)
James D. Meindl
Low power microelectronics: retrospect and prospect. Proc. IEEE 83 (4) (1995)
Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl
Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE J. Solid State Circuits 29 (2) (1994)
James D. Meindl
Gigascale integration (GSI) technology. SC (1991)
James D. Meindl
Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. ICCD (1991)
Kenneth A. Pickar, James D. Meindl
Scanning the issue. Proc. IEEE 74 (12) (1986)