Azeez J. Bhavnagarwala

Publication Activity (10 Years)

Years Active: 1996-2008
Publications (10 Years): 0

Publications

Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43 (4) (2008)
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47 (2-3) (2003)
Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo
Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectron. Reliab. 42 (9-11) (2002)
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD (2001)
Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits 36 (4) (2001)
Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8 (3) (2000)
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI (2000)
Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
Minimum supply voltage for bulk Si CMOS GSI. ISLPED (1998)
Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
Circuit techniques for low-power CMOS GSI. ISLPED (1996)