A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing.
Azeez J. BhavnagarwalaStephen KosonockyCarl RadensYuen H. ChanKevin StawiaszUma SrinivasanSteven P. KowalczykMatthew M. ZieglerPublished in: IEEE J. Solid State Circuits (2008)