George Gristede

Publication Activity (10 Years)

Years Active: 1990-2020
Publications (10 Years): 6

Top Topics

Parameter Tuning

Weakly Supervised

Top Venues

Publications

Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108 (12) (2020)
Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits (2020)
Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits (2018)
Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED (2018)
Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni
A synthesis-parameter tuning system for autonomous design-space exploration. DATE (2016)
Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni
A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs. RES4ANT@DATE (2016)
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
POWER8 design methodology innovations for improving productivity and reducing power. CICC (2014)
Matthew M. Ziegler, George Gristede, Victor V. Zyuban
Power reduction by aggressive synthesis design space exploration. ISLPED (2013)
Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich
The opportunity cost of low power design: a case study in circuit tuning. ISLPED (2009)
Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS (2009)
Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. Integr. 38 (3) (2005)
Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
Characterization of logic circuit techniques for high leakage CMOS technologies. ACM Great Lakes Symposium on VLSI (2004)
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47 (2-3) (2003)
W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED (2001)
George Gristede, Wei Hwang
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI (2000)
Wei Hwang, Rajiv V. Joshi, George Gristede
A scannable pulse-to-static conversion register array for self-timed circuits. IEEE J. Solid State Circuits 35 (1) (2000)
Charles A. Zukowski, George Gristede, Albert E. Ruehli
Measuring Error Propagation in Waveform Relaxation Algorithms. ICCAD (1990)