Anda Mocuta

Publication Activity (10 Years)

Years Active: 2005-2019
Publications (10 Years): 9

Top Topics

Cmos Technology

Metal Oxide Semiconductor

Schottky Barrier

Shape Variability

Top Venues

Publications

Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC (2019)
Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marco Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS (2019)
Philippe J. Roussel, Adrian Chasin, Steven Demuynck, Naoto Horiguchi, Dimitri Linten, Anda Mocuta
New methodology for modelling MOL TDDB coping with variability. IRPS (2018)
Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta
SRAM designs for 5nm node and beyond: Opportunities and challenges. ICICDT (2017)
Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. ESSDERC (2017)
Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. ICICDT (2017)
F. M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta
On the ballistic ratio in 14nm-Node FinFETs. ESSDERC (2017)
D. Verreck, Anne S. Verhulst, Bart Soree, Nadine Collaert, Anda Mocuta, Aaron Thean, Guido Groeseneken
Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors. ESSDERC (2016)
Thomas Chiarella, S. Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, A. De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC (2016)
Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean
Impact of fin shape variability on device performance towards 10nm node. ICICDT (2015)
Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean
Modeling FinFET metal gate stack resistance for 14nm node and beyond. ICICDT (2015)
Geert Eneman, A. De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. ICICDT (2015)
Romain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Christian Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. ICICDT (2015)
M. Ali Pourghaderi, Anda Mocuta, Aaron Thean
Nonparabolicity and confinement effects of IIIV materials in novel transistors. ICICDT (2015)
Romain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son
Assessment of SiGe quantum well transistors for DRAM peripheral applications. ICICDT (2015)
Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, A. Steegen
Holisitic device exploration for 7nm node. CICC (2015)
Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design (2005)