Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Trong Huynh BaoAnabela VelosoSushil SakharePhilippe MatagneJulien RyckaertManu PerumkunnilDavide CrottiFarrukh YasinAlessio SpessotArnaud FurnémontGouri Sankar KarAnda MocutaPublished in: DAC (2019)