Luc Rijnders

Publication Activity (10 Years)

Years Active: 1989-2016
Publications (10 Years): 1

Top Topics

Data Management

Rapid Development

Silicon On Insulator

Top Venues

Publications

Thomas Chiarella, S. Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, A. De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC (2016)
Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo
System Level Architecture Exploration for Reconfigurable Systems On Chip. FPL (2006)
Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. SCOPES (2003)
Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková
High-performance flexible all-digital quadrature up and down converter chip. IEEE J. Solid State Circuits 36 (3) (2001)
Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
A Hardware Virtual Machine for the Networked Reconfiguration. IEEE International Workshop on Rapid System Prototyping (2000)
Robert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková
High-performance flexible all-digital quadrature up and down converter chip. CICC (2000)
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. DATE (1999)
Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
A Programming Environment for the Design of Complex High Speed ASICs. DAC (1998)
Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. ED&TC (1997)
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man
Timing optimization by bit-level arithmetic transformations. EURO-DAC (1995)
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (9) (1989)
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. DAC (1989)