A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS.
Viki SzortykaQixian ShiKuba RaczkowskiBertrand ParvaisMaarten KuijkPiet WambacqPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- power consumption
- nm technology
- power supply
- cmos technology
- high speed
- low power
- hd video
- silicon on insulator
- sampling algorithm
- power dissipation
- feature selection
- random sampling
- sample size
- power reduction
- monte carlo
- clock frequency
- packet loss
- circuit design
- sampling strategy
- video transmission
- low cost
- analog vlsi
- vlsi circuits
- frequency band