A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS.

Annachiara Spagnolo Bob Verbruggen Stefano D'Amico Piet Wambacq

Published in: ESSCIRC (2014)

Keyphrases

power consumption
power supply
hd video
cmos technology
nm technology
low power
analog to digital converter
silicon on insulator
high definition
low cost
high speed
power management
single chip
analog vlsi
data flow
real time
circuit design