21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS.
Viki SzortykaQixian ShiKuba RaczkowskiBertrand ParvaisMaarten KuijkPiet WambacqPublished in: ISSCC (2014)
Keyphrases
- power consumption
- nm technology
- power supply
- hd video
- cmos technology
- low power
- high speed
- power reduction
- feature selection
- low cost
- silicon on insulator
- sampling algorithm
- monte carlo
- sampling methods
- random sampling
- sample size
- metal oxide semiconductor
- sampling strategy
- power plant
- packet loss
- video transmission
- high definition
- low voltage
- clock frequency