Anne-Johan Annema

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 17

Top Topics

Hardware Implementation

Axiomatic Characterization

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Alexander S. Delke, Thomas J. Hoen, Anne-Johan Annema, Yanyu Jin, Jos Verlinden, Bram Nauta
A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz. IEEE J. Solid State Circuits 58 (9) (2023)
Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Alexander S. Delke, Anne-Johan Annema, Mark S. Oude Alink, Yanyu Jin, Jos Verlinden, Bram Nauta
A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. IEEE J. Solid State Circuits 56 (11) (2021)
Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
Theory and Implementation of a Load-Mismatch Protective Class-E PA System. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2020)
Alexander S. Delke, Anne-Johan Annema, Mark S. Oude Alink, Yanyu Jin, Jos Verlinden, Bram Nauta
A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C. CICC (2020)
Ali Ghahremani, Anne-Johan Annema, Bram Nauta
A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits (2019)
Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC (2019)
Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53 (7) (2018)
Ali Ghahremani, Anne-Johan Annema, Bram Nauta
Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement. IEEE J. Solid State Circuits 53 (5) (2018)
Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
Augmentation of Class-E PA Reliability under Load Mismatch Conditions. ICECS (2018)
Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC (2017)
Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta
Hardware Implementation Overhead of Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC (2017)
Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta
A 30fJ/comparison dynamic bias comparator. ESSCIRC (2017)
Vishal Agarwal, Anne-Johan Annema, Satadal Dutta, Raymond J. E. Hueting, Lis K. Nanver, Bram Nauta
Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs. ESSDERC (2016)
Erik Olieman, Anne-Johan Annema, Bram Nauta
An Interleaved Full Nyquist High-Speed DAC Technique. IEEE J. Solid State Circuits 50 (3) (2015)
Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta
On the Minimum Number of States for Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Erik Olieman, Anne-Johan Annema, Bram Nauta
, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. VLSIC (2014)
Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta
A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. IEEE J. Solid State Circuits 48 (2) (2013)
Wei Cheng, Anne-Johan Annema, Gerard Wienk, Bram Nauta
A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. IEEE J. Solid State Circuits 48 (10) (2013)
Benaoumeur Senouci, Anne-Johan Annema, Mark J. Bentum, Hans G. Kerkhoff
Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design. DSD (2012)
Anne-Johan Annema, George Goksun
bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS. ISSCC (2012)
Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta
A wideband IM3 cancellation technique for CMOS attenuators. ISSCC (2012)
Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Jeroen A. Croon, Bram Nauta
RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Wei Cheng, Anne-Johan Annema, Jeroen A. Croon, Bram Nauta
Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2011)
Anne-Johan Annema, Paul Veldhorst, Gerben Doornbos, Bram Nauta
A sub-1V bandgap voltage reference in 32nm FinFET technology. ISSCC (2009)
Paul Veldhorst, George Goksun, Anne-Johan Annema, Bram Nauta, Berry A. J. Buter, Maarten Vertregt
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. ESSCIRC (2009)
Wei Cheng, Anne-Johan Annema, Jeroen A. Croon, Dirk B. M. Klaassen, Bram Nauta
A general weak nonlinearity model for LNAs. CICC (2008)
Wei Cheng, Anne-Johan Annema, Bram Nauta
A multi-step P-cell for LNA design automation. ISCAS (2008)
Mustafa Acar, Anne-Johan Annema, Bram Nauta
Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. ISSCC (2008)
Mustafa Acar, Anne-Johan Annema, Bram Nauta
Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. ISCAS (2007)
Mustafa Acar, Anne-Johan Annema, Bram Nauta
Analytical Design Equations for Class-E Power Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2007)
Mustafa Acar, Anne-Johan Annema, Bram Nauta
Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. ICECS (2006)
Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. IEEE J. Solid State Circuits 40 (8) (2005)
Bram Nauta, Anne-Johan Annema
Analog/RF circuit design techniques for nanometerscale IC technologies. ESSCIRC (2005)
T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta
An audio FIR-DAC in a BCD process for high power class-D amplifiers. ESSCIRC (2005)
Anne-Johan Annema, Bram Nauta, Ronald van Langevelde, Hans Tuinhout
Analog circuits in ultra-deep-submicron CMOS. IEEE J. Solid State Circuits 40 (1) (2005)
Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. Microelectron. Reliab. 45 (3-4) (2005)
Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema
Reducing quantization noise with recursive Sigma Delta modulators. ISCAS (1) (2004)
Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. IEEE J. Solid State Circuits 36 (3) (2001)
Anne-Johan Annema, Govert Geelen, Peter C. de Jong
5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. CICC (2000)
Anne-Johan Annema
Low-power bandgap references featuring DTMOSTs. IEEE J. Solid State Circuits 34 (7) (1999)
Anne-Johan Annema, Hans Wallinga
Analog weight adaptation hardware. Neural Process. Lett. 2 (3) (1995)
Anne-Johan Annema, Klaas Hoen, Hans Wallinga
Learning behavior and temporary minima of two-layer neural networks. Neural Networks 7 (9) (1994)