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A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply.

Harijot Singh BindraAnne-Johan AnnemaGerard WienkBram NautaSimon M. Louwsma
Published in: CICC (2019)
Keyphrases
  • high speed
  • low power
  • power consumption
  • independent and identically distributed
  • cmos technology
  • learning algorithm
  • multiscale
  • low cost
  • parameter estimation
  • delay insensitive