Harijot Singh Bindra

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 10

Top Topics

Synthetic Aperture Radar

Bias Variance Decomposition

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yuting Shen, Hanyue Li, Harijot Singh Bindra, Eugenio Cantatore, Pieter Harpe
A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation. IEEE Trans. Circuits Syst. II Express Briefs 70 (5) (2023)
Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Harijot Singh Bindra, Jeroen Ponte, Bram Nauta
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. ISSCC (2022)
Joeri Lechevallier, Harijot Singh Bindra, Ronan A. R. van der Zee, Bram Nauta
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. IEEE J. Solid State Circuits 56 (8) (2021)
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits (2019)
Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC (2019)
Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53 (7) (2018)
Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC (2017)
Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC (2017)
Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta
A 30fJ/comparison dynamic bias comparator. ESSCIRC (2017)
Harijot Singh Bindra, Shouri Chatterjee, Kaushik Saha, Taranjit Kukal
Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation. ISCAS (2013)