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A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.

Harijot Singh BindraChris E. LokinDaniël SchinkelAnne-Johan AnnemaBram Nauta
Published in: IEEE J. Solid State Circuits (2018)
Keyphrases
  • power consumption
  • low power
  • input data
  • cmos technology
  • low cost
  • high speed
  • image quality
  • dynamic environments
  • motion vectors
  • noise reduction
  • random noise
  • real time
  • noisy data
  • high density
  • gaussian noise
  • noise model