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A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.
Rajesh Inti
Sudip Shekhar
Ganesh Balamurugan
James E. Jaussi
Clark Roberts
Tzu-Chien Hsueh
Bryan Casper
Published in:
VLSIC (2015)
Keyphrases
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bi directional
high speed
power consumption
lane detection
traffic flow
low cost
detection algorithm
associative memory
cmos technology
road surface
lane departure
hough transform
low power
query expansion
neural network
low voltage
english chinese
nm technology