Peter Buchmann

Publication Activity (10 Years)

Years Active: 1998-2016
Publications (10 Years): 2

Top Venues

ISSCC

ESSCIRC

IEEE J. Solid State Circuits

ICASSP

ETH Zurich, Switzerland (PHD)

Education History

ETH Zurich, Switzerland

PHD

Publications

Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. ISSCC (2016)
Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC (2015)
Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese
at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. ISSCC (2014)
Pier Andrea Francese, Thomas Toifl, Peter Buchmann, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits 49 (11) (2014)
Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC (2014)
Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC (2014)
Martin L. Schmatz, Rik Jongerius, Gero Dittmann, Andreea Anghel, Ton Engbersen, Jan van Lunteren, Peter Buchmann
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation. ICASSP (2014)
Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits 48 (12) (2013)
Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC (2013)
Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC (2013)
Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits 47 (4) (2012)
John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, W. R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47 (12) (2012)
Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel
A 28Gb/s source-series terminated TX in 32nm CMOS SOI. ISSCC (2012)
Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC (2012)
Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. ISSCC (2011)
Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE J. Solid State Circuits 44 (2) (2009)
Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. IEEE J. Solid State Circuits 44 (11) (2009)
Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. IEEE J. Solid State Circuits 43 (12) (2008)
Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. ISSCC (2008)
Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. ISSCC (2007)
Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. ISSCC (2007)
Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits 41 (4) (2006)
Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss
A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links. IEEE J. Solid State Circuits 40 (12) (2005)
Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg, John F. Ewen, John F. Gilsdorf, Philippe Hauviller, Andreas Herkersdorf, Jean-Claude Le Garrec, Wolfram W. Lemppenau, Ben Parker, Dale J. Pearson, Joseph M. Pereira, Dominique Plassat, Scott K. Reynolds, Hans R. Schindler, André Steimle, David J. Webb, Albert X. Widmer
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. IEEE J. Solid State Circuits 36 (1) (2001)
Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb
Design Methodology for a Large Communication Chip. IEEE Des. Test Comput. 17 (3) (2000)
Albert Geukes, Peter Buchmann
Reproduction of Hypermedia Lectures. WebNet (1998)

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Publication Activity (10 Years)

Top Topics

Top Venues

Peter Buchmann